python-pythondata-cpu-vexriscv 2022.08-4
| Architecture: | any |
|---|---|
| Repository: | Extra-Staging |
| Description: | Python module containing verilog files for vexriscv cpu (for use with LiteX) |
| Upstream URL: | https://github.com/litex-hub/pythondata-cpu-vexriscv |
| License(s): | MIT |
| Maintainers: | Orphan |
| Package Size: | 2.3 MB |
| Installed Size: | 25.0 MB |
| Last Packager: | Jelle van der Waa |
| Build Date: | 2024-11-16 17:23 UTC |
| Signed By: | Jelle van der Waa |
| Signature Date: | 2024-11-16 17:23 UTC |
| Last Updated: | 2024-11-16 17:32 UTC |
Dependencies (2)
- python (staging)
- python-setuptools (staging) (make)
Required By (1)
- python-litex (check)